Xilinx V2.1 Manuale Utente Pagina 3
- Pagina / 148
- Indice
- SEGNALIBRI
- Xilinx System 1
- Generator v2.1 1
- About This Manual 2
- Additional Resources 3
- Conventions 4
- Contents 5
- Chapter 6 Auxiliary Files 7
- Chapter 1 8
- Introduction 8
- Arithmetic Data Types 12
- Hardware Handshaking 13
- Chapter 2 15
- Xilinx Blockset Overview 15
- Valid and Invalid Data 17
- Port Data Types 17
- Licensed Cores 18
- Versions 19
- Arithmetic Type 20
- Generate Core 20
- Precision 21
- Number of Bits 21
- Overflow and Quantization 21
- Override with Doubles 21
- Sample Period 22
- Chapter 3 23
- Xilinx Blocks 23
- Addressable Shift Register 26
- Black Box 28
- Block Interface 30
- Constant 31
- Down Sample 36
- Get Valid Bit 37
- Parallel to Serial 39
- Register 40
- Reinterpret 42
- Serial to Parallel 43
- Set Valid Bit 45
- Up Sample 50
- Communication 52
- Depuncture 54
- Interleaver Deinterleaver 55
- Puncture 58
- RS Decoder 59
- RS Encoder 63
- Viterbi Decoder 68
- Xilinx LogiCore 70
- Xk() xm()W 75
- Block Timing 77
- Accumulator 81
- Inverter 85
- Relational 90
- SineCosine 93
- Threshold 95
- MATLAB I/O 96
- Gateway In 97
- Gateway Out 99
- Quantization Error Blocks 101
- Dual Port RAM 102
- Block Parameters Dialog Box 104
- Xilinx LogiCORE 105
- Single Port RAM 110
- State Machine 114
- Moore State Machine 116
- Chapter 4 127
- Using Black Boxes 128
- Black Box window 129
- System Clock Period 133
- Multicycle Path Constraints 133
- Important Issues 136
- 138 Xilinx Development System 138
- • sysgen.log - log file 138
- System Generator 138
- Chapter 5 139
- Using the Xilinx Software 139
- Implementing your design 140
- Using an EDIF software flow 143
- Simulation 143
- MXE libraries 144
- Chapter 6 146
- Auxiliary Files 146
- Perl scripts 147
- 148 Xilinx Development System 148
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