Xilinx SP605 Manuale Utente Pagina 3
- Pagina / 74
- Indice
- SEGNALIBRI
- SP605 Hardware 1
- User Guide 1
- Revision History 2
- Date Version Revision 3
- Table of Contents 5
- Appendix A: References 6
- Appendix D: SP605 Master UCF 6
- About This Guide 7
- Additional Support Resources 8
- SP605 Evaluation Board 9
- Features 10
- Block Diagram 11
- Related Xilinx Documents 12
- Detailed Description 12
- Configuration 14
- References 15
- I/O Voltage Rails 16
- 3. SPI x4 Flash 19
- 4. Linear BPI Flash 21
- 6. USB JTAG 25
- 7. Clock Generation 26
- UG526_08_100509 27
- UG526_09_100509 27
- SMA Connectors (Differential) 28
- SMA MGT Connectors 29
- MGT REFCLK 29
- P4 PCIe Edge Connector 31
- Pin Number Pin Name 31
- 10. SFP Module Connector 33
- 12. USB-to-UART Bridge 36
- 13. DVI CODEC 37
- 14. IIC Bus 38
- IIC External Access Header 39
- 8-Kb NV Memory 39
- 15. Status LEDs 41
- Ethernet PHY Status LEDs 42
- FPGA INIT and DONE LEDs 43
- 16. User I/O 44
- User Pushbutton Switches 45
- User DIP Switch 46
- User SIP Header 47
- User SMA GPIO 48
- 17. Switches 49
- UG526_21 _092409 50
- UG526_22 _092409 50
- SDMX-4-X 51
- 19. Power Management 55
- Caution! 56
- Onboard Power Regulation 57
- Configuration Options 60
- Appendix A: References 62
- Appendix B 63
- Appendix C 65
- SP605 Master UCF 67
- Appendix D: SP605 Master UCF 68
- Regulatory and Compliance 73
- Information 73
- Markings 74
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